IC carrier for use with an IC handler

ABSTRACT

An IC carrier for loading thereon and transporting a device under test is used in an IC handler. The IC carrier is capable of easily and reliably loading thereon and positioning in place a device under test even the device under test having a reduced pitch between lead pins thereof. A box-like housing open in the top is formed and the bottom wall thereof has two generally parallel contact holes in the form of elongated slots, these two contact holes being spaced from each other by a spacing corresponding to that between two arrays of lead pins of the device under test. Each of the contact holes has a length corresponding to that of the associated lead pin array and a width sufficient to receive the associated lead pin array. Carrier guides are formed one adjacent each of opposite longitudinal ends of each of the contact holes and extend upwardly to a predetermined height from the bottom floor of the housing. The distance between the side walls of the carrier guides opposing each other transversely of the length of the contact holes is selected such that the device under test is accommodated between the opposed side walls of the carrier guides. The socket for applying electric signals to the device under test has two rows of socket terminals spaced apart by substantially the same distance as the spacing between the two contact holes, each row containing socket terminals of the same number and same pitch as the pins of the corresponding lead pin array of the device under test. Insulating thin plate members are interposed between adjacent socket terminals of each of said socket terminal rows. The socket terminals are adapted to be inserted into the contact holes and be electrically connected with the lead pins of the device under test during the electric testing.

TECHNICAL FIELD

This invention relates to an IC handler for use in a semiconductordevice testing apparatus (IC tester), and more particularly, to ICcarriers for transporting devices under test (each is generally referredto as DUT) in an IC handler.

BACKGROUND ART

An IC tester for testing semiconductor devices (generally, ICs, i.e.,semiconductor integrated circuits) usually employs an IC handlerintegrally incorporated therein for transporting IC carriers loaded withICs under test or trays carrying thereon IC carriers loaded with ICsunder test from a loader section to a testing zone, and upon the testbeing completed, transporting them from the testing zone to an unloadersection where the tested ICs are sorted into corresponding categoriesbased on the data of the test results.

An example of the prior art IC handler called "forced horizontaltransporting system" is shown in the form of a flow chart in FIG. 1. TheIC handler 10 comprises a loader section 11 where ICs 15 under testcarried on a customer (user) tray 13 are transferred and reloaded onto atest tray 14 capable of withstanding high/low temperatures, an unloadersection 12 where tested ICs 15 are sorted, transferred and reloaded oncustomer trays 13 from a test tray 14, and a constant temperaturechamber 20 including a testing zone 21 for receiving and testing the ICsfrom the loader section 11. The test trays 14 are moved in a circulatingmanner from and back to the loader section 11 sequentially through theconstant temperature chamber 20 and the unloader section 12. Morespecifically, the test tray 14 loaded with ICs 15 to be tested istransported from the loader section 11 to a soak chamber 22 within theconstant temperature chamber 20 where the ICs 15 on the test tray 14 areheated or cooled to a predetermined constant temperature. Generally, thesoak chamber 22 is adapted to store a plurality of (say, ten) test trays14 stacked one on another such that a test tray 14 newly received fromthe loader section 11 is stored at the bottom of the stack while theuppermost test tray is carried to the testing zone 21. The ICs 15 to betested are heated or cooled to a predetermined constant temperaturewhile the test tray 14 is moved from the bottom to the top of the stackwithin the soak chamber 22, and the heated or cooled ICs 15 togetherwith the test tray 14 having the heated or cooled ICs 15 loaded are thentransported while maintained at the constant temperature from the soakchamber 22 to the testing zone 21 where each of the ICs under test isbrought into electrical contact with an IC socket (not shown) disposedin the testing zone 21 and electric characteristics of the ICs aremeasured. Upon completion of the test, the ICs 15 together with the testtray 14 are transported from the testing zone 21 to an exit chamber 23where they are restored to the ambient temperature. Like the soakchamber 22, the exit chamber 23 is also adapted to store test trays inthe form of a stack. In one embodiment the ICs 15 under test may bebrought back to the ambient temperature as the associated test tray ismoved sequentially from the top to the bottom of the stack within theexit chamber 23. Thereafter, the ICs 15 under test as carried on thetest tray 14 are passed to the unloader section 12 where the tested ICsare sorted into categories based on the data of the test results andtransferred from the test tray 14 onto the corresponding customer trays13. The test tray 14 emptied in the unloader section 12 is deliveredback to the loader section 11 where it is again loaded with ICs 15 to betested from the customer tray 13 to repeat the same steps of operation.It is to be noted that the transfer of ICs 15 under test between thecustomer tray 13 and the test tray 14 is typically effected by suctiontransport means utilizing a vacuum pump which may pick up one to severalICs at a time for the transfer.

While the IC handler 10 illustrated in FIG. 1 is of the type which isconfigured to transport ICs under test together with the tray on whichthe ICs are loaded, IC handlers of the type adapted to transport ICsunder test individually are also currently used.

As described above, an IC under test as loaded on the IC carrier istransported by the IC handler 10 from the loader section 11 to thetesting zone 21 whence upon completion of the test they are passed tothe unloader section 12. It should here be pointed out that surfacemounting type ICs received in flat packages each of which has two arraysof leads extending from opposite sides thereof (flat package type ICs)as represented by the SOP (small outline package) and TSOP (thin smalloutline package) are tested for their electric characteristics in thetesting zone by that each of the ICs is electrically connected with anIC socket as it is carried on an IC carrier. There are a variety of flatpackage type ICs with respect to the inter-lead array spacing (whichrefers to the spacing between two arrays of lead pins here in thisspecification), the number of pins, and the inter-pin spacing (whichrefers here to the spacing between adjacent lead pins in the lead pinarray). To handle ICs of such various types of pin arrangement forelectric testing, the IC handler has to exchange all IC carriers usedfor ICs of one specified type for IC carriers dedicated to Ics ofanother specified type whenever the inter-lead array spacing, the numberof pins and/or the inter-pin spacing of the IC to be tested are varied.Moreover, with an increase in the integration density (higher thedensity of integration) of IC, the number of leads protruding from an ICpackage is increased with a decrease in the pin spacing (reduction inthe pin pitch). To take one example, an IC having the inter-pin spacingof 0.5 mm has so small an inter-lead gap (gap between opposed edges oftwo adjacent lead pins) as about 0.2 mm (because each of the lead pinshas a thickness or width of about 0.3 mm).

A typical example of the conventional IC carrier is illustrated in FIGS.2-4. As shown in FIG. 2, the IC carrier 30 comprises a box-like housing31 which has a generally rectangular shape in plan and is open in thetop thereof. A flat package type IC is accommodated within the box-likehousing 31. Formed in the bottom wall of the box-like housing 31 are tworows of contact holes 32 corresponding to the inter-lead array spacing,the inter-pin spacing and the number of pins of the flat package type ICto be housed. The contact holes 32 of each row are defined by thin platecarrier guides 33 two more than the number of leads of the flat packagetype IC to be accommodated, the carrier guides being spaced apart atpredetermined intervals. As seen in FIGS. 3 and 4, these carrier guides33 are positioned to project upwardly by a predetermined distance abovethe plane of the bottom floor of the housing 31, and the transversedimension (width) of the flat package type IC (the distance between thetwo opposed sides of IC from which the leads protrude) is accommodatedbetween the opposed side walls defined by the two rows of carrier guides33 whereby the transverse (width-wise) movement of the flat package typeIC is constrained, that is, the transverse position of the flat packagetype IC is determined in the housing. Alternatively, separate carrierguides having a positioning function which serves to transversely locatea flat package type IC to be received may be provided, and both thecarrier guides 33 and the separate carrier guide may be used. Thelongitudinal dimension (length) of the bottom floor of the housing 31 issized so as to correspond to the longitudinal dimension of the flatpackage type IC (the distance between the two opposed sides of IC fromwhich no leads protrude) to thereby determine the longitudinal positionof the flat package type IC in the housing. It is to be noted that theside walls of the housing 31 are tapered as illustrated to facilitatethe insertion of the flat package type IC.

All of the rectangular housings 31 in all types of IC carrier have theirexterior structures of the same shape and same size so that they canutilize the transport mechanism in the IC handler in common whereas theinterior structures there of vary from one to another IC carrier so asto accommodate various flat package type ICs differing in the exteriorconfiguration and the number of pins. It is for this reason thatwhenever the inter-lead array spacing, the number of pins and/or theinter-pin spacing of the flat package type IC to be tested are changed,the IC handler exchanges one type of IC carrier for another having acorresponding proper construction. A great number of, say 50 to 200 suchIC carriers 30 are used in an IC handler.

The contact holes 32 are provided to permit the electrical testing to beeffected on the IC under test while it is loaded on the IC carrier 30 inthe testing zone 21. As illustrated in FIG. 5, when an IC (flat packagetype IC) 40 under test is deposited on the IC carrier 30, the IC leads41 thereof are guided by the carrier guides 33 to overlie thecorresponding contact holes 32. It is thus to be understood that thecarrier guides 33 not only act as positioning guides to guide the ICleads 41 of the IC 40 under test into the respective contact holes 32,but also serve to prevent any lateral displacement of the IC leads 41and short-circuit between adjacent IC leads as the upper end portions ofthe carrier guides 33 are interposed into respective gaps betweenadjacent IC leads 41.

The IC socket 50 for use in the electric testing in the testing zone 21is provided with two rows of socket terminals (contacts) 51 spaced apartby the same distance as the spacing between the two rows of carrierguides 33, the socket terminals 51 of each row being of the same numberand same pitch as the carrier guides 33 of the corresponding row. Whenthe electric testing is to be carried out, the socket terminals 51 areinserted into the respective contact holes 32 of the IC carrier 30.During the test an IC lead hold-down mechanism 60 presses on the leads41 of the IC 40 under test, as illustrated in FIG. 6, in order to insureelectric contact between the leads 41 and the respective socketterminals 51 inserted into the contact holes 32. The IC lead hold-downmechanism 60 comprises a pair of insulative comb-like push members 61having fingers equal in number and pitch to the leads 41 of the IC 40under test, the arrangement being such that the fingers of each of thepush members 61 will push down on the horizontally out-turned outer endportions of the corresponding leads 41 of the IC 40 under test to insurethe electric contact with the socket terminals 51 in the contact holes32.

As indicated above, with a recent enhancement in the integration densityof IC, the more and more leads does the IC package have protrudingtherefrom with a corresponding decrease in the pin spacing. There havebeen evolved numerous ICs having an inter-lead gap (gap between opposededges of two adjacent lead pins of each lead pin array of an IC)narrower than 0.2 mm. It follows that the thickness of the carrierguides 33 constituting partition walls for separating the contact holes32 of the IC carrier 30 from each other must also be reduced to lessthan 0.2 mm, but it would be very difficult to fabricate such thincarrier guides. In addition, since the material of which the carrierguides 33 are made (normally molded integrally with the IC carrier 33)is an insulating material such as a plastic resin or the like, thincarrier guides are so weak in their strength, bringing forth thedrawbacks that they may be broken when the IC under test is loaded onthe IC carrier 30, that during the loading the IC leads 41 are apt tohit the carrier guides 33 to be bent thereby due to the reduced pitchbetween the pins, and that it takes a longer time to load the IC carrierwith an IC.

DISCLOSURE OF THE INVENTION

It is an object of this invention to provide an IC carrier which iscapable of positioning an IC to be tested in a stable and positivemanner even if the IC has a narrow inter-pin spacing.

Another object of this invention is to provide an IC carrier which iseasy to manufacture and inexpensive.

According to the present invention, an IC carrier for use in an IChandler is provided which comprises: a box-like housing open in the topfor accommodating a device under test therein; two generally parallelcontact holes in the form of elongated slots formed in the bottom wallof the box-like housing, the two contact holes being spaced from eachother by a spacing corresponding to that between the two arrays of leadpins of a device under test to be accommodated, each of the contactholes having a length corresponding to that of the corresponding leadpin array and a width sufficient to receive the corresponding lead pinarray; and carrier guides one formed adjacent each of oppositelongitudinal ends of each of the contact holes and extending upwardly toa predetermined height from the bottom floor of the housing, thedistance between the side walls of the carrier guides opposing eachother transversely of the length of the contact holes being selectedsuch that the device under test is accommodated between the opposed sidewalls of the carrier guides.

With the construction of this invention as described above, theprovision of the contact holes in the form of elongated slots having asimple shape makes it easy to manufacture the IC carrier, and yetpermits the lead pins of the device under test to be readily insertedinto the contact holes. In addition, it is to be appreciated that thesame IC carrier may be used on another type of IC package having a finerpitch between lead pins protruding therefrom as long as the length ofthe pin array is the same, eliminating the need for exchanging the ICcarrier for another, and hence enhancing the operating efficiency.Moreover, since carrier guides are disposed at four locations one ateach of the opposite longitudinal ends of each contact hole to positionthe device under test, it is possible to form relatively large guides,independently of the pitch between the lead pins. This may provide thecarrier guides with a substantial strength so that there is nolikelihood of the guides being damaged even if they are formed with ataper. It is thus easy to provide the carrier guides with a taper. Whatis more, upon being loaded on the IC carrier, the device under test isrestrained with respect to its position in the lead pin array directionby the pins at the opposite extreme ends of each lead pin array engagingwith the carrier guides and with respect to the transverse position in adirection perpendicular to the direction of lead pin array by the sidewalls of the IC package along the perpendicular direction engaging withthe corresponding sides of the carrier guides, whereby once loaded onthe IC carrier, the device under test is held in position in a stablemanner to insure good electric contact between the leads and therespective socket terminals for the electric testing, resulting inenhanced reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatical illustration showing the whole constructionof a prior art IC handler of the forced horizontal transporting systemin the form of a flow chart;

FIG. 2 is a plan view showing an example of the prior art IC carrierused in the prior art IC handler;

FIG. 3 is a generally cross-sectional view of the IC carrier of FIG. 2taken along the line III--III;

FIG. 4 is a generally cross-sectional view of the IC carrier of FIG. 2taken along the line IV--IV;

FIG. 5 is an outline view showing the IC carrier of FIG. 2 in across-section to illustrate how an IC under test loaded on the ICcarrier is tested;

FIG. 6 is an outline view as seen from the right hand side of FIG. 5;

FIG. 7 is a plan view showing an embodiment of the IC carrier accordingto this invention;

FIG. 8 is a generally cross-sectional view of the IC carrier of FIG. 7taken along the line VIII--VIII;

FIG. 9 is a generally cross-sectional view of the IC carrier of FIG. 7taken along the line IX--IX;

FIG. 10 is an outline view showing the IC carrier of FIG. 7 in across-section to illustrate how an IC under test loaded on the ICcarrier is tested; and

FIG. 11 is an outline view as seen from the right hand side of FIG. 10.

BEST MODES FOR CARRYING OUT THE INVENTION

One embodiment of the present invention will be described in detailswith reference to the accompanying drawings.

FIGS. 7-9 illustrate the construction of an embodiment of the IC carrieraccording to this invention. As shown in FIG. 7, the IC carrier 30comprises a box-like housing 31 which has a generally rectangular shapein plane and is open in the top thereof. A flat package type IC isaccommodated within the box-like housing 31. Formed in the bottom wallof the housing 31 are two generally parallel contact holes 35 in theform of elongated slots formed in the bottom wall of the housinglongitudinally of the housing, the two contact holes being spaced fromeach other by a spacing corresponding to the inter-lead array spacing ofthe flat package type IC. Carrier guides 36 in the shape of a squarepost are formed one adjacent each of the opposite longitudinal ends ofeach contact hole 35.

As shown in FIGS. 8 and 9, these four carrier guides 36 are positionedsubstantially symmetrically about a longitudinal straight line passingthrough the center of the bottom wall of the housing 31 (substantiallysymmetrically about a transverse (width-wise) straight line passingthrough the center as well in the illustrated embodiment) and projectupwardly by a predetermined distance above the bottom floor of thehousing 31.

The longitudinal and transverse spacings between the longitudinally andtransversely opposed carrier guides 36, respectively are selected suchthat as is best seen in FIG. 11, the width dimension of the flat packagetype IC 40 is accommodated between the opposed side walls of the guides36 in the width-wise direction of the IC carrier 30 (transversely of thecontact holes) and that as is best seen in FIG. 10, each of the arraysof IC lead pins 41 of the flat package type IC 40 is accommodatedbetween the opposed side walls of the guides 36 in the longitudinaldirection of the IC carrier 30 (with the outer side surfaces of the pinsat the opposite extreme ends of each lead pin array being substantiallyin contact with the associated sides of the guides 36). It is thus to beunderstood that both the transverse and longitudinal movements of theflat package type IC 40 are constrained by these four carrier guides 36,that is, the transverse and longitudinal positions of the flat packagetype IC 40 are determined by the four carrier guides 36. It is notedthat the four carrier guides 36 have their longitudinally opposed sidewalls formed with a taper 36a extending downwardly and inwardly from thetop thereof as illustrated so that the pins at the opposite extreme endsof each lead pin array of the flat package type IC 40 may not interferewith the corresponding tops of the carrier guides 36. Similarly, thewidth-wise opposed side walls of the four carrier guides 36 are formedwith a taper extending downwardly and inwardly from the top towardbottom thereof as illustrated so as to facilitate the loading of the ICto be tested onto the IC carrier.

Due to the provision of the contact holes 35 in the form of elongatedslots, the IC carrier 30 according to this invention permits easyinsertion of the IC leads into the contact holes without the possibilitythat the IC leads may hit the carrier guides to get bent or that anunexpectedly longer time may be required for the insertion as may be thecase with the prior art. In addition, the same IC carrier may be used onanother type of IC package having lead pin arrays protruded therefromthe inter-pin spacing of which is reduced as long as the length of thelead pin array is the same, eliminating the need for exchanging the ICcarrier for another, and hence enhancing the operating efficiency.Furthermore, as the IC leads are inserted into the contact holes 35, thetapered side surfaces 36a of the carrier guides 36 which engage with thepins at the opposite extreme ends of the lead pin arrays serve to guidethe IC leads stably and smoothly into the contact holes 35.Consequently, there is little possibility of the IC leads of beingdeformed or hitting the carrier guides during the loading. Additionally,when the IC is loaded on the IC carrier, the longitudinal position ofthe IC (in the direction of the lead pin array) is determined by thepins at the opposite extreme ends of the lead pin arrays engaging withthe carrier guides 36 while at the same time the transverse position ofthe IC in a direction perpendicular to the direction of the lead pinarray is determined by the side walls of the IC package along theperpendicular direction engaging with the corresponding sides of thecarrier guides 36. The loaded IC is thus held in position in a stablemanner to insure good electric contact between the leads and therespective socket terminals for the electric testing, resulting inenhanced reliability.

On top of that, since the carrier guides 36 are disposed at fourlocations one at each of the opposite longitudinal ends of each contacthole to position the IC, it is possible to form guides of a relativelylarge size (thickness and width), thoroughly independently of the pitchbetween the pins of the IC leads. This permits easy fabrication of thecarrier guides, leading to reduction of cost. Furthermore, it ispossible to provide the carrier guides with a substantial strength sothat there is no fear of the guides being damaged even if they areformed with a taper. It is also easy to provide the carrier guides witha taper 36a. In addition, since the contact holes 36 are simpleelongated slots and no high accurate processing or working is required,it is easy to fabricate the IC carrier thereby contributing to reducingthe cost thereof as a whole.

The IC 40 under test (flat package type IC) loaded on the IC carrier 30having the structure as described above is transported by the IC handlerto the testing zone where the electric test is carried out. The socket50 for applying electric signals to the IC 40 under test carried on theIC carrier 30 has two rows of socket terminals (contacts) 51 spacedapart from each other by substantially the same spacing between thecontact holes 36, each row containing the socket terminals of the samenumber and same pitch as the pins of the corresponding lead pin array ofthe IC 40 under test so that, when tested, the two rows of socketterminals 51 are inserted into the corresponding contact holes 36 of theIC carrier 30. In order to insure that electric contact is maintainedbetween the leads 41 of the IC 40 under test and the correspondingsocket terminals 51 of the socket 50 inserted into the contact holes 36during the test, the IC lead hold-down mechanism 60 presses down on thehorizontally bent tip ends of the leads 41 of the IC 40 under test asdescribed hereinbefore with reference to the prior art.

There is a possibility that some of the socket terminals 51 of thesocket 50 pressed by the leads may get crooked under the pressure fromthe IC lead hold-down mechanism 60 to cause a short-circuit betweenadjacent socket terminals. For this reason, according to this invention,insulating terminal guides 52 in the form of a thin plate are interposedbetween adjacent socket terminals 51 to prevent any short-circuit frombeing formed between the adjacent socket terminals. The terminal guides52 may be of the same shape and size and are more or less shorter inheight than the socket terminals 51 so as not to interfere with electriccontact between the leads 41 of the IC 40 and the socket terminals 51.The terminal guides 52 may be termed insulating members (means)interposing between adjacent socket terminals rather than guides in thatthey act not only to hold the socket terminals in their upright positionto permit good electric contact with the IC leads, but also to preventany short-circuit from being caused between adjacent socket terminals.No substantial mechanical strength is required of the terminal guides 52since they are neither in the least interfered by the IC carrier 30 norcontacted by the IC leads 41 when electric contact is establishedbetween the socket terminals 51 and the IC leads 41. Consequently, theterminal guides 52 may be extremely reduced in thickness as required, sothat it is possible to readily accommodate any reduced pitch between theIC leads. Evidently, there is no manufacturing problem. While the use ofinsulating thin plate terminal guides 52 between adjoining socketterminals 51 may cause a slight increase in the cost of manufacture, thenumber of sockets is much smaller than that of IC carriers, and henceany reduction in the cost of the IC carrier advantageously leads to asubstantial decrease in the cost of the entire IC handler.

We claim:
 1. An IC handler arranged such that an IC under test havingtwo opposed arrays of lead pins projecting therefrom is transported asloaded on an IC carrier to a testing zone where electric signals areapplied through a socket to the IC under test loaded on the IC carrierfor performing an electric testing, said IC carrier comprising:abox-like housing (30) open in the top for accommodating a device undertest therein; two generally parallel contact holes (35) in the form ofelongated slots formed in the bottom wall of said box-like housing, saidtwo contact holes being spaced from each other by a spacingcorresponding to that between the two lead pin arrays of said deviceunder test to be accommodated, each of the contact holes having a lengthcorresponding to the corresponding lead pin array and a width sufficientto receive the corresponding lead pin array; and carrier guides (36) oneformed adjacent each of opposite longitudinal ends of each of saidcontact holes and extending upwardly to a predetermined height from thebottom floor of said housing, the distance between the side walls ofsaid carrier guides opposing each other transversely of the length ofthe contact holes being selected such that the device under test isaccommodated between said opposed side walls of the carrier guides. 2.The IC handler according to claim 1 wherein said socket for applyingelectric signals to the IC under test has two rows of socket terminals(51) spaced apart by substantially the same distance as the spacingbetween said two contact holes, each row containing socket terminals ofthe same number and same pitch as the pins of the corresponding lead pinarray of the IC under test, insulating thin plate members (52) beinginterposed between adjacent pins of each of said lead pin arrays, andsaid two rows of socket terminals being adapted to be inserted into thecorresponding contact holes during the electric testing.
 3. The IChandler according to claim 2 wherein said insulating thin plate membersare shorter in height than said socket terminals.
 4. The IC handleraccording to claim 1 wherein said carrier guides have each of theirlongitudinally opposed side walls formed with a taper (36a) extendingdownwardly from the top thereof.
 5. The IC handler according to claim 1wherein said carrier guides are positioned substantially symmetricallyabout a straight line passing through the center of the bottom wall ofsaid housing and substantially parallel to said contact holes.